Biography
Prof. Partha S Mallick
Prof. Partha S Mallick
School of Electrical Engineering, Vellore Institute of Technology, India
Title: Performance of CNTs as interconnects in VLSI circuits
Abstract: 
Performance of highly scaled down interconnects in integrated circuits is a major cause of concern among microelectronics engineers and scientists. As the cross sectional size of interconnects is reduced to a few tens of nano-meters, many reliability problems arise in copper based interconnects, which is used currently in ICs. However, the last decade has seen extensive research by academia and industry alike, in developing carbon nanotube (CNT) based interconnects that have many advantages over existing copper interconnects. Many research groups including our own, have studied the possibilities of using CNTs as interconnects. After the first prototype of MWCNT based interconnects is fabricated and tested at 1GHz in 2008, it became very clear that the time when integrated circuits work on CNT based interconnects is closer than anticipated.

Here, the major performance factors that determine the applicability of CNTs as interconnects are presented. Factors like delay, coupling capacitance, crosstalk and peak noise in interconnects are discussed in detail. We have earlier proposed different methods to reduce delay, crosstalk and peak noise in coupled CNT interconnects. Three main possible methods are discussed here: (i) use of semiconducting CNTs at CNT interconnect periphery, (ii) use of air-gaps in-between CNT interconnects and (iii) use of triangular cross section CNT bundles as interconnects. Results from these three methods show similar trends in reducing delay, coupling capacitance, crosstalk and noise. Interestingly, each method has its own advantages from fabrication point of view. So, a mix of all three methods wherever suitable, will be the best choice in improving the overall performance in integrated circuits.
Biography: 
Prof (Dr.) Partha S Mallick is working as a Sr. Professor of Electronics Engineering, in VIT University, India. He was the Dean of School of Electrical Engineering (2011-15). Dr Mallick led various research teams and developed "Online Lab in Microelectronics", "Monte Carlo Simulator of Compound Semiconductors", "Nanostructured MIM Capacitor", "Low cost Electric Fencers" and published 110 research papers in different reputed Journals. Dr Mallick is a regular reviewer different Journals of IET, IEEE Transactions, Bentham Science, Elsevier and Taylors & Francis. Dr Mallick is a speaker of Elsevier Research Connect Forum, India. Dr Mallick organized the 1st World Summit on Science, Engineering and Technology at University of Cambridge, UK in 2018 and the 2nd Summit jointly with Indiana University-Purdue University (IUPUI), Indianapolis, USA during October 3-5, 2019. He is finding new materials and technology for future nano scale electronics, VLSI circuit engineering and interconnects. Dr Mallick published more than 100 research papers in Journals and Conferences of International repute. Some of his published books and book chapters are: “Crosstalk Analysis in Carbon Nanotube Interconnects” Springer, UK(2020), “Anodic MIM Capacitors” (book chapter), IET, UK(2016), “Matlab and Simulink – Introduction to Applications”, Scitech Publishers, India (2010).